The present invention concerns the use and operation of computer memory (e.g., DRAM) in general; and, more specifically, to a method for dynamically adjusting a DRAM page closing policy and memory controller and circuitry for performing the method.
Memory controller circuits can be used in a variety of computer systems (e.g., desktop personal computers, notebook computers, personal digital assistants, etc.) to facilitate the computer system""s processor in accessing memory chips. These memory chips generally include the main memory of the computer system, which typically comprises a plurality of dynamic random access memory (DRAM) chips, which may comprise, for example, synchronous DRAM (SDRAM) chips, extended data out (EDO) DRAM chips, Rambus (R)DRAM chips, DDR (double data rate) SDRAM chips, etc. The memory controller provides a memory interface for connecting to one or more of such DRAM chips, and a system interface to connect to the system processor(s). The memory controller uses these interfaces to route data between the processor and the DRAM chips using appropriate address and control signals.
Generally, the DRAM chips used in modern computers are organized in groups and mounted on one or more xe2x80x9cmemory modules.xe2x80x9d The most common memory modules in use today are known as DIMMs (Dual In-line Memory Modules), which comprise a small circuit board having a 168-pin double-sided connector at its base on which a plurality of DRAM chips and one or more controller chips are mounted. (Alternatively, the DRAM chips may have embedded controller circuitry built in.) Other common memory modules include 144-pin Small Outline DIMMS (SODIMMS), which are used in laptop computers, and SIMMs (Single In-line Memory Modules), as well a various other types of configurations.
Typically, a modem DIMM can store 32, 64, 128, 256, and 512 megabytes (Mb) of memory, which corresponds to the total memory capacity of the memory chips on the DIMM. The memory on each DRAM chip is logically configured in a memory array comprising a plurality of rows and columns of memory xe2x80x9ccells.xe2x80x9d Each memory cell has a particular address, and stores a single bit of data. This memory array is then logically partitioned into one or more xe2x80x9cbanksxe2x80x9d of memory. In many DRAM chips, there are four banks of memory. In modem DRAM chips, such as page-mode, EDO, and SDRAM chips, memory is accessed on a xe2x80x9cpagexe2x80x9d basis, wherein the memory cells for a given row within a bank comprises a xe2x80x9cpagexe2x80x9d of memory. Memory pages typically comprise 512, 1024 (1K), 2048 (2K), 4098 (4K), 8196 (8K), 16392 (16K) or 32,768 (32K) bits of data.
Accessing DRAM is generally a multi-step process that is performed by the memory controller in the following manner. First, the page or pages corresponding to the requested data or instructions are identified. Once the page or pages are known, the appropriate bank corresponding to the page(s) is/are determined. The memory controller then xe2x80x9copensxe2x80x9d the appropriate bank(s) and appropriate page(s). Generally, the particular page(s) of data requested will initially be in one of three states: page hit, page empty, or page miss. If the state is a page hit, the desired page is already loaded into a bank of sense amplifiers (amps) corresponding to the memory bank the page is stored in. If a page empty state is encountered, data corresponding to the desired page will need to be loaded into an appropriate sense amp bank via an xe2x80x9cactivatexe2x80x9d command before it can be accessed. If the state of the bank is a page miss, the specified bank contains a different page of data than that requested. This existing page will first be required to be xe2x80x9cclosed,xe2x80x9d which comprises writing it back to the memory array using a xe2x80x9cprechargexe2x80x9d command, and then the appropriate page will need to be loaded into the sense amp bank using the activate command.
The foregoing three states have an impact on access latency. A page hit state means the page is ready to be accessed with no additional latency. A page empty state requires an activate command, while a page miss requires both pre-charge and activate commands, each of which may take one or more clock cycles. The actual penalty (i.e., delay) for each type of access will depend on the memory technology, memory organization and architecture, and on other rules specific to each memory technology. The general rule however is that a page hit is fastest, and a page empty is slower, and a page miss is slowest.
Typical existing page-management policies include xe2x80x9cpage-open,xe2x80x9d xe2x80x9cpage-closexe2x80x9d and timer mechanisms. Under the page-open policy, pages are left open until they need to be closed due to a page miss (or need to be closed due to some other memory architecture rule such as the need to refresh them). Under page-close policy, pages are closed with a xe2x80x9cprechargexe2x80x9d command as soon as possible after the current access completes. With timer mechanisms, xe2x80x9cidlexe2x80x9d timers are used to determine that memory in general, or a specific bank in particular, have been idle for N clock cycles. If N clock cycles have expired with no accesses, the page(s) is/are closed. The counters may be per bank, in which case only that bank""s pages will be closed when the timer expires. Other implementations may have timer per row or for all of the system memory, in which case all pages in a row or in all of the system memory may be closed when the timer expires.